Manufacturers and designers of integrated circuits continue to relentlessly decrease the size of integrated-circuit features, such as transistors and signal lines, and correspondingly increase the density at which features can be fabricated within integrated circuits. However, manufacturers and designers have begun to approach fundamental physical limits that prevent further decreasing feature sizes in integrated circuits fabricated by conventional photolithography techniques. Recent research efforts have turned to new, non-photolithography-based techniques for fabricating nanoscale electronics that represent a significant decrease in feature sizes from currently available, submicroscale electronics fabricated by currently available high-resolution photolithographic techniques.
In one approach to designing and fabricating nanoscale electronics, nanowires with molecular-scale widths can be fabricated on a surface of a suitable substrate. Nanowire junctions representing the closest point of contacts between adjacent nanowires may be fabricated to have properties of configurable resistors, switches, diodes, transistors, and other familiar electronic components of integrated circuits. In other approaches, nanowire-crossbar arrays including multiple layers of nanowires can be formed. The grid-like nanowire crossbars provide a two-dimensional array of nanowire junctions that can be configured to form a variety of different types of electronic devices or electronic components. In addition to being used to form nanowire junctions, nanowires have also found utility in sensors, as electrical interconnects, and in a number of other electrical and optical applications.
Nanowires can be fabricated using nanoimprint lithography. In nanoimprint lithography, a layer of nanoimprint resist made from a thermoplastic material or a photocurable polymer is deposited on a substrate. A nanoimprinting mold imprints a nanowire pattern in the nanoimprint resist. When the nanoimprint resist is a curable resist, the nanoimprint resist is cured with the nanoimprinting mold embedded within the nanoimprint resist. After curing, the nanoimprinting mold is removed and an anisotropic etching process is used to remove residue nanoimprint resist from the base of individual trenches defined in the nanoimprint resist that serve as a template for individual nanowires. Then, a metallic material is deposited within the trenches, for example, by evaporation, sputtering, or plating. The nanoimprint resist is then removed, leaving polycrystalline-metallic nanowires formed on the substrate.
As the lateral dimensions of polycrystalline-metallic nanowires continue to decrease, material defects in the polycrystalline-metallic nanowires can significantly influence the electrical properties of the polycrystalline-metallic nanowires. Grain boundaries and other defects within polycrystalline-metallic nanowires can significantly increase the resistivity of the polycrystalline-metallic nanowires. High-resistivity polycrystalline-metallic nanowires can deleteriously decrease the speed at which nanoscale-electronic devices operate. Therefore, researchers and developers of nanoscale-electronic devices continue to seek techniques for fabricating high-quality, low-resistivity nanowires so that nanowires with reduced lateral dimensions can be utilized in nanoscale electronics without compromising important performance characteristics.